Current mirrors can be used in analog circuits for providing current bias or signals to a variety of circuits. The output impedance of the current mirror can affect the accuracy of the current provided by the current mirror. High output impedance in current mirrors is desired for accurate replication of currents. Cascode transistors can be used to obtain high output impedance. A current mirror may also be characterized as having an output voltage swing. High voltage swing in current mirrors can be desired for accurate operation, such as with low power supply voltages, and for increased voltage signal amplitudes, which can improve the accuracy of analog circuitry utilizing the current mirrors.
Current mirrors are building blocks used in integrated circuits. In CMOS technologies, current mirrors operate on the principle that if the gate-source voltages of two identical transistors are equal, then their drain currents are equal. A current mirror's output impedance can be represented by the slope of the output current when graphed against the output voltage—the smaller the slope, the higher the output impedance. A high output impedance can be desirable for a current mirror because parameters of the circuits with which the current mirror is used can be detrimentally affected by a low output impedance (e.g., the common-mode rejection ratio of a differential transistor pair can be worse with low output impedance of a current mirror sourcing or sinking current to the differential pair). A current mirror's compliance voltage range parameter provides a measure of the output voltage range over which the current mirror can maintain a constant output current.
One approach to achieving high output impedance for a current mirror is to use one or more cascode transistors in series with an output transistor of the current mirror. While the cascode transistors themselves do not consume current, additional circuits that consume current can be needed provide bias voltages for their gates. Moreover, if cascode gate bias voltages are not well-controlled for ensuring transistor operation at the lower end or edge of the saturation region, a substantial reduction in the compliance voltage range can occur.